The 7 Domains Behind Every PCB Stack-Up (and Why They Fight Each Other)¶
A stack-up isn't just "pick the number of layers." It's seven engineering disciplines pulling in different directions — and getting them to converge is the actual job.
If you've ever wondered what a stack-up designer actually thinks about, or if you do this work and want a clear overview of where the discipline is heading, this article breaks it down.
What stack-up design actually involves
A stack-up is a set of interdependent engineering decisions that collectively determine whether a board meets its electrical, thermal, mechanical, and regulatory requirements.
Layer count and assignment. How many copper layers, and what does each carry — signal, ground plane, power plane? A 28 GHz phased array might need 8-10 layers with ground planes adjacent to every signal layer for controlled impedance. Layer assignment directly affects impedance control, crosstalk isolation, and power delivery.
Material selection. Standard FR-4 is commonly used below roughly 3 GHz. Above that, designers choose between Rogers 4350B (Dk = 3.48, Df = 0.0037), MEGTRON6 (Dk = 3.4, Df = 0.002), or Isola Astra MT77 — each with different loss tangent, Tg, CTE, and moisture absorption. Material choice directly impacts insertion loss, signal quality, and long-term reliability.
Impedance targeting. 50 Ω single-ended for RF. 90-100 Ω differential for high-speed digital. These targets require solving field equations for microstrip, stripline, and coplanar waveguide geometries. Every material or thickness change shifts the impedance, making this inherently iterative.
Signal integrity. Crosstalk between adjacent traces. Propagation delay and skew for timing-critical buses. Insertion loss from copper roughness at mmWave frequencies. Glass weave Dk variation causing intra-pair skew on differential pairs.
Power integrity. Interplanar capacitance between power/ground plane pairs acts as distributed decoupling. Target impedance profiles across frequency determine whether the PDN can deliver clean voltage under transient loads. Plane pair spacing and dielectric properties set the baseline for the entire power delivery network.
Thermal management. Thermal via arrays under power components. Spreading resistance through copper planes. Warpage prediction from CTE mismatch between layers. Barrel stress analysis for plated through-holes in applications requiring thousands of thermal cycles.
Compliance. IPC-2221 conductor spacing, IPC-4101 material qualification, IPC-6012 performance classes, MIL-STD-883, MIL-PRF-31032. Environmental regulations: UL 94V-0 flammability, RoHS 3, REACH SVHC tracking. Each standard has its own acceptance criteria and documentation requirements.
Seven domains. Most teams handle them with a combination of dedicated tools, material datasheets, fab house consultation, and accumulated experience.
Where the workflow gets challenging
The tools available today are capable — impedance calculators are accurate, material databases exist, compliance checklists are well-documented. The challenge isn't any single tool. It's the interaction between domains.
Cross-domain coupling. Adjusting a dielectric thickness to hit an impedance target changes the interplanar capacitance (affecting PDN impedance), the plane separation (affecting crosstalk), and potentially the thermal path through the board. These relationships are well-understood physically, but tracking them manually across separate tools requires discipline and attention.
Design rationale preservation. Standard export formats — Gerber, ODB++ — capture the geometry but not the engineering reasoning. Why was Rogers 4350B chosen over MEGTRON6? What impedance target drove the trace width on Layer 3? That context typically lives in design reviews, email threads, or the designer's memory. When someone inherits a project months later, reconstructing the reasoning takes real effort.
Manufacturing feedback loop. When a board returns from fabrication with yield data, connecting that outcome back to specific stack-up decisions in a structured way is uncommon. Most teams track yield in spreadsheets that aren't linked to the design files. Experienced engineers build intuition about what works, but that knowledge is hard to transfer.
None of these are unsolvable problems — experienced teams develop workflows to manage them. But they represent areas where better tooling could reduce the manual overhead.
What would an integrated approach look like?
Imagine a stack-up editor where all seven domains share a common model and update together. When you change a dielectric thickness, the impedance, crosstalk, propagation delay, PDN, thermal, and compliance results all recalculate from the same source data. No re-entering parameters across tools.
A few things that would matter in a tool like this:
A material library with compatibility data. Not just Dk/Df values, but frequency-dependent curves, thermal properties, and CTE data — with automatic flagging of CTE mismatch between adjacent laminates, Tg concerns for lead-free reflow, and moisture absorption considerations.
Impedance solvers across geometries. Microstrip, embedded microstrip, stripline, broadside-coupled, and edge-coupled differential — with protocol presets for DDR4, PCIe Gen4/5, USB 3.x, and HDMI 2.1. Ideally an inverse solver that calculates trace geometry for a given target impedance.
Design rationale that travels with the export. Whether it's ODB++, Gerber, IPC-2581, or a simulator format, the export should carry metadata: impedance targets, solver results, material selection reasoning, compliance status. A deterministic fingerprint linking a design revision to its manufacturing outcomes would make yield tracking far more practical.
The goal of a tool like this wouldn't be to replace the engineer's judgment. It would be to reduce the bookkeeping so you can focus on the actual design trade-offs.
The rest of this series goes deeper on individual domains: materials and impedance in Part 2, signal integrity in Part 3, power integrity in Part 4, thermal engineering in Part 5, compliance in Part 6, test coupons and exports in Part 7, and design intelligence in Part 8.
Which of these seven domains causes the most unexpected problems in your designs? I'm curious what resonates with other engineers.
This is Part 1 of an 8-part series on PCB stack-up design. Next: "Material Selection and Impedance Targeting."
References
Materials - Rogers Corporation. RO4000 Series High Frequency Circuit Materials — Data Sheet (RO4350B). - Panasonic Electronic Materials. MEGTRON 6 (R-5775) Multi-layer Circuit Board Material — Data Sheet. - Isola Group. Astra MT77 Laminate and Prepreg — Product Data Sheet.
IPC standards - IPC-2221B, Generic Standard on Printed Board Design. IPC, 2012. - IPC-2581, Generic Requirements for Printed Board Assembly Products Manufacturing Description Data and Transfer Methodology. IPC. - IPC-4101E, Specification for Base Materials for Rigid and Multilayer Printed Boards. IPC. - IPC-6012E, Qualification and Performance Specification for Rigid Printed Boards. IPC.
Military / aerospace - MIL-STD-883L, Test Method Standard: Microcircuits. U.S. Department of Defense. - MIL-PRF-31032, Performance Specification: Printed Circuit Board / Printed Wiring Board, General Specification For. U.S. Department of Defense.
Safety, environmental, and regulatory - UL 94, Standard for Tests for Flammability of Plastic Materials for Parts in Devices and Appliances. Underwriters Laboratories. - Directive (EU) 2015/863 amending Annex II to Directive 2011/65/EU (RoHS 3). - Regulation (EC) No 1907/2006 (REACH) — Substances of Very High Concern (SVHC) Candidate List, European Chemicals Agency (ECHA).