Component Placement & Layout Generation Rules¶

📋 Overview¶

This document defines the mandatory rules for component placement and layout generation in the PCB Stackup Generator. All code modifications must comply with these rules to ensure manufacturability, RF performance, thermal management, and assembly reliability.

🎯 1. Component Placement Zones & Strategy¶

1.1 Zoning Layout¶

┌─────────────────────────────────────────┐
│  DC/Power Components Zone (y=50mm)     │ ← Isolation from RF
│  ┌─────┐  ┌─────┐  ┌─────┐             │
│  │ LDO │  │ REG │  │ PWR │             │
│  └─────┘  └─────┘  └─────┘             │
├─────────────────────────────────────────┤
│                                         │
│  RF Signal Chain Zone (y=100mm)        │ ← Centered, horizontal
│  ┌─────┐  ┌─────┐  ┌─────┐  ┌─────┐   │
│  │ VCO │→ │ DRV │→ │ PA  │→ │ FLT │→  │
│  └─────┘  └─────┘  └─────┘  └─────┘   │
│                                    ┌───┤
│                                    │ J │ ← Connector
│                                    └───┤
└─────────────────────────────────────────┘

1.2 Component Classification Rules¶

MANDATORY: All components must be classified using these exact criteria:

RF Components (Zone: y=100mm)¶

rf_functions = ['vco', 'amplifier', 'mixer', 'filter', 'lna', 'pa']
rf_part_numbers = ['adf', 'tqp', 'sky', 'qpa', 'hmc', 'bfcn']

DC/Power Components (Zone: y=50mm)¶

dc_functions = ['power', 'regulator', 'ldo', 'converter']
dc_part_numbers = ['adp', 'ltc', 'tps']

Connectors (Zone: y=100mm, at endpoints)¶

connector_functions = ['connector']
connector_part_numbers = ['sma', 'u.fl']

1.3 Block Diagram Order Enforcement¶

CRITICAL: Signal chain components MUST maintain this exact sequence:

VCO → Driver → PA → Filter → Connector

📐 2. Component Spacing Rules (DFM-Based)¶

2.1 Minimum Spacing Requirements¶

Component Type	Minimum Spacing	Reason
Base (Any)	4.0mm	DFM manufacturability + schematic readability
RF-to-RF	15.0mm	Interference prevention + signal integrity
Thermal	8.0mm	Heat dissipation + thermal management

2.2 Package Size Database¶

MANDATORY: Use these exact dimensions for spacing calculations:

PACKAGE_SIZES = {
    # QFN Packages
    'QFN-16': (3.0, 3.0),
    'QFN-20': (4.0, 4.0), 
    'QFN-24': (4.0, 4.0),

    # LFCSP Packages
    'LFCSP-16': (3.0, 3.0),
    'LFCSP-24': (4.0, 4.0),
    'LFCSP-32': (5.0, 5.0),

    # Other Packages
    'DFN-8': (3.0, 2.0),
    'SOT-89': (2.5, 4.5),
    'MSOP-8': (3.0, 3.0),
    'TSSOP-16': (5.0, 4.4),

    # Passives
    '0805': (2.0, 1.25),
    '0603': (1.6, 0.8),

    # Connectors
    'SMA-F-PCB-RA': (6.35, 6.35),
    'U.FL-R-SMT-1': (2.5, 2.5),
}

2.3 Thermal Clearance Rules¶

def calculate_thermal_clearance(component):
    function = component.get('function', '').lower()

    if 'pa' in function or 'power amplifier' in function:
        return 2.0  # Power amplifiers need extra thermal space
    elif 'regulator' in function or 'ldo' in function:
        return 1.0  # Power regulators need moderate thermal space
    else:
        return 0.0  # Standard components

🏭 3. Manufacturing (DFM) Constraints¶

3.1 PCB Fabrication Limits¶

Parameter	Minimum Value	Notes
Via Drill	0.25mm	TTM Technologies standard
Annular Ring	0.125mm	Class 2 IPC standard
Trace Width	0.25mm	35μm copper
Trace Spacing	0.25mm	35μm copper
Copper to Edge	0.3mm	Board edge clearance

3.2 Silkscreen Rules¶

Silkscreen to Mask: Minimum clearance maintained
Component References: Must be visible after assembly (not under components)
Silkscreen to Copper: No overprinting on copper features
Text Height: Minimum readable size for assembly

📡 4. RF-Specific Design Rules¶

4.1 Signal Chain Optimization¶

RF_DESIGN_RULES = {
    'critical_path_length': 'minimize',
    'signal_sequence': 'block_diagram_order',
    'isolation': 'rf_separated_from_dc',
    'ground_return': 'continuous_plane',
    'impedance_control': '50_ohm_±10%'
}

4.2 Material Selection by Application¶

THERMAL_DESIGN_RULES = {
    'CONSUMER': {
        'max_operating_temp': 70,
        'required_tg_margin': 25,
        'max_thermal_resistance': 50,
        'recommended_materials': ['FR4', 'FR408']
    },
    'INDUSTRIAL': {
        'max_operating_temp': 85,
        'required_tg_margin': 25,
        'max_thermal_resistance': 40,
        'recommended_materials': ['FR408', 'FR408HR']
    },
    'RF_MICROWAVE': {
        'max_operating_temp': 85,
        'required_tg_margin': 40,
        'max_thermal_resistance': 25,
        'recommended_materials': ['RO4350B', 'RO4450T', 'MEGTRON6']
    },
    'HIGH_POWER': {
        'max_operating_temp': 100,
        'required_tg_margin': 50,
        'max_thermal_resistance': 15,
        'recommended_materials': ['RO6035HTC', 'IS680']
    }
}

🔧 5. Via Placement Optimization¶

5.1 Thermal Via Patterns¶

Pattern I: Regular Grid¶

def regular_grid_pattern(available_area, via_specs):
    """Standard thermal via placement"""
    # Calculate grid dimensions
    # Center grid in available space
    # Ensure equal edge distances

Pattern II: Staggered Grid¶

def staggered_grid_pattern(available_area, via_specs):
    """Offset alternate rows for better heat distribution"""
    # Apply row offset = (via_diameter + spacing) / 2
    # Maintain centering

Pattern III: Maximum Density¶

def hexagonal_pattern(available_area, via_specs):
    """Hexagonal close packing for optimal density"""
    # row_height = via_diameter * sin(60°)
    # Use hexagonal grid placement

5.2 Via Placement Validation¶

MANDATORY CHECKS: - [ ] Equal edge distance from boundaries - [ ] Minimum via-to-via spacing maintained
- [ ] All vias within safe boundary - [ ] No via-to-via spacing violations

🏷️ 6. Reference Designator Rules¶

6.1 Smart Prefix Assignment¶

MANDATORY: Use these exact prefix rules:

def get_reference_prefix(component):
    function = component.get('function', '').lower()
    part_number = component.get('partNumber', '').lower()

    if 'filter' in function or 'bfcn' in part_number:
        return 'FL'  # Filters
    elif 'connector' in function or 'sma' in part_number:
        return 'J'   # Connectors  
    elif 'oscillator' in function or 'vco' in function:
        return 'Y'   # Oscillators/VCOs
    else:
        return 'U'   # Default for ICs/amplifiers

6.2 Reference Sequence¶

Components must be numbered in block diagram order: - Y1: VCO (first in chain) - U1: Driver amplifier - U2: Power amplifier - FL1: Filter - J1: Output connector

🔬 7. Validation and Testing Requirements¶

7.1 Placement Validation Checklist¶

EVERY placement must pass these checks:

def validate_placement(components):
    checks = {
        'block_diagram_order': verify_signal_chain_sequence(),
        'minimum_spacing': verify_component_clearances(),
        'zone_compliance': verify_rf_dc_zones(),
        'thermal_clearance': verify_thermal_spacing(),
        'reference_prefixes': verify_designator_rules()
    }
    return all(checks.values())

7.2 Expected Test Results¶

✅ Block diagram order: CORRECT (exact sequence preserved)
✅ Component spacing: MET (>= minimum requirements)  
✅ RF zone placement: CORRECT (y=100mm centered)
✅ DC zone placement: CORRECT (y=50mm above)
✅ File generation: SUCCESS (schematic + PCB files)

🚀 8. Implementation Requirements¶

8.1 Core Files That Must Comply¶

backend/utils/kicad_export.py - Primary placement engine
Backend component API / backend/categorized_databases/ - Component specifications (frontend has no local component database)

8.2 Mandatory Functions¶

Every placement implementation MUST include:

def classify_component_type(component: Dict) -> str:
    """Classify component for zoning"""

def calculate_required_spacing(comp1: Dict, comp2: Dict) -> float:
    """Calculate minimum spacing between components"""

def validate_placement_rules(components: List) -> bool:
    """Validate all placement rules are met"""

⚡ 9. Enforcement Mechanisms¶

9.1 Code Review Checklist¶

Before merging any placement-related code:

Follows component zoning rules
Uses mandatory spacing requirements
Maintains block diagram order
Includes thermal clearance calculations
Passes all validation tests
Uses correct reference designators

9.2 Automated Testing¶

REQUIRED: All placement code must include tests that verify: - Component spacing meets minimums - RF/DC zones are correct - Block diagram order is preserved - Reference designators follow rules

📚 10. References and Standards¶

IPC-2221: Generic Standard on Printed Board Design
IPC-2152: Standard for Determining Current Carrying Capacity
TTM Technologies: PCB fabrication capabilities
Sierra Circuits: DFM guidelines and best practices

🔄 11. Version Control¶

Version	Date	Changes
1.0	2025-01-09	Initial comprehensive rules documentation

⚠️ CRITICAL: Any code modification that affects component placement MUST comply with ALL rules in this document. Non-compliance will result in manufacturability issues, RF performance degradation, or assembly failures.