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Material Selection and Impedance Targeting (and Why You Have to Solve Them Together)

You can hit 50 Ω on FR-4, MEGTRON6, or Rogers 4350B. The trace just gets wider, narrower, or sits on a different dielectric thickness. So in a narrow sense, material and impedance are independent — pick the laminate, then adjust geometry until the solver lands on target.

But that's only true if impedance is your only constraint. Once you add insertion loss at your operating frequency, available standard thicknesses, fab capability, CTE compatibility, and cost, the two decisions become tightly coupled. A material that lets you hit 50 Ω cleanly may have unacceptable loss above 10 GHz. A target trace width may demand a dielectric thickness your fab doesn't stock for the laminate you picked. That's why experienced designers iterate between them rather than treating either as fixed.

The dielectric constant determines impedance. The loss tangent determines signal quality. The glass transition temperature determines manufacturing compatibility. The CTE determines reliability. And the cost determines whether the project is viable.

If you've ever wondered why fab houses push back on certain stack-up requests, or you do this work and want a clearer mental model of how the trade-offs interact, this article breaks it down.

The material landscape

PCB laminates span a wide range of electrical and mechanical properties. The choice depends primarily on operating frequency, reliability requirements, and budget.

FR-4 variants (Dk ~ 4.2-4.5, Df ~ 0.015-0.025). The workhorse of the industry. Works well for digital designs below roughly 3 GHz. Multiple grades exist — standard Tg (130°C), mid-Tg (150°C), and high-Tg (170°C+) for lead-free reflow compatibility. Low-cost, widely available, and well-understood by every fab house.

Mid-range low-loss (Dk ~ 3.3-3.8, Df ~ 0.003-0.008). Materials like Panasonic MEGTRON4 and MEGTRON6, Isola I-Tera MT40, and various "enhanced FR-4" formulations. These bridge the gap between FR-4 and RF-grade materials. MEGTRON6 (Dk = 3.4, Df = 0.002) has become a popular choice for designs in the 5-15 GHz range where FR-4 loss is unacceptable but Rogers pricing isn't justified.

RF-grade laminates (Dk ~ 2.9-3.6, Df ~ 0.001-0.004). Rogers 4350B (Dk = 3.48, Df = 0.0037), Rogers 4003C (Dk = 3.55, Df = 0.0027), Isola Astra MT77 (Dk = 3.0, Df = 0.0017). Designed for microwave and mmWave applications. Tighter Dk tolerance, lower loss, and better high-frequency stability — but at 5-20x the cost of FR-4.

PTFE-based (Dk ~ 2.1-2.5, Df < 0.001). Rogers RT/duroid, Taconic TLY. The lowest loss materials available, used for satellite, radar, and mmWave above 40 GHz. Challenging to process — requires specialized fab capability and different drilling, plating, and lamination procedures.

Frequency-dependent properties

A common mistake is treating Dk and Df as constants. They're not. Both vary with frequency, and the variation matters above ~5 GHz.

Dk typically decreases slightly with frequency for most laminates — a 10-20% drop between 1 GHz and 20 GHz is common for FR-4. The implication: an impedance calculation using the 1 GHz Dk value will be slightly wrong at 10 GHz. For tightly toleranced designs (±5%), that error can push you out of spec.

Df increases with frequency for most materials. This means insertion loss grows faster than a simple linear extrapolation would suggest. A material that looks acceptable at 5 GHz may have unacceptable loss at 15 GHz.

Reputable material suppliers publish Dk/Df curves across frequency. Using these curves rather than single-point values is essential for designs above a few GHz.

A related note: above roughly 10 GHz, copper surface roughness becomes as significant as Df in determining insertion loss. The skin effect concentrates current within roughly 0.5 µm of the conductor surface at those frequencies, so any roughness on the order of the skin depth — common with standard reverse-treated foil — adds appreciable loss beyond what bulk Df would predict. RTF (reverse-treated foil), VLP (very low profile), and HVLP (hyper very low profile) copper grades exist specifically to address this, with HVLP becoming the default for designs above ~25 GHz.

Design Dk vs. Process Dk

There's another Dk subtlety that catches people off guard: the value on the datasheet may not be the one you should use for impedance modeling. Manufacturers like Rogers publish two distinct values — a "Process Dk" measured under standard test conditions (typically a clamped-stripline resonator per IPC TM-650 2.5.5.5) and a "Design Dk," which is an averaged value calibrated specifically against measured trace impedance.

The two differ because Process Dk reflects the bulk laminate, while Design Dk accounts for how the resin and glass weave actually distribute around a copper trace in a finished stack-up. For Rogers 4350B, the Process Dk is around 3.66 at 10 GHz, but the Design Dk used for stripline impedance calculation is closer to 3.48. Plugging the Process value into an impedance solver can introduce a 3-5% error — small in isolation, but enough to push a tightly toleranced design (±5%) out of spec.

The rule of thumb: if your laminate vendor publishes a Design Dk, use that for impedance work. Reserve Process Dk for bulk-material simulation, dielectric loading studies, or analyses where the trace isn't sitting in a real glass-weave environment.

The fiber weave effect

A related Dk subtlety hits high-speed differential pairs: glass weave inhomogeneity. The glass fibers in a typical prepreg (style 7628, 2116, 1080) have a Dk around 6.0, while the resin between them sits closer to 3.0-3.5. A trace running across the board alternates between regions dominated by glass bundles and regions dominated by resin — and the local Dk shifts accordingly.

For a single-ended trace, this averages out over length. For a differential pair routed at small angles to the weave, one trace can sit predominantly on glass bundles while the partner sits on resin — producing different propagation velocities and intra-pair skew. At 28 Gbps and above, the resulting timing error is enough to close the eye.

Two standard mitigations. First, rotate the routing relative to the weave (typically 10-20° off-axis) so both traces see the same average dielectric over their length. Second, specify a "spread glass" or "mechanically spread" prepreg — styles 1067, 1078, and 1086 are common — where the weave is opened up to flatten the resin/glass density variation. Most high-speed laminates intended for ≥10 Gbps applications include spread-glass options as a standard offering.

Hybrid stack-ups and CTE mismatch

Cost optimization often leads to mixed-material stack-ups — RF-grade laminates on the outer layers where high-frequency signals route, and FR-4 on inner layers carrying low-speed signals or power. This is practical and widely used, but it introduces CTE mismatch.

The Z-axis CTE of FR-4 is roughly 40-70 ppm/°C (above Tg), while Rogers 4350B is around 32 ppm/°C. When these materials are laminated together and thermally cycled, differential expansion creates stress — particularly at plated through-hole barrels that span the full board thickness.

Matching CTE between adjacent layers, or at least keeping the mismatch within acceptable limits for your reliability class, is a stack-up design decision that's easy to overlook when focused on electrical properties.

Impedance: five geometries

Impedance targeting in a PCB stack-up involves five primary transmission line geometries:

Microstrip. Trace on an outer layer, ground plane below, with soldermask on top. The most accessible geometry — easy to probe, well-characterized. But the soldermask adds 1-2 ohms of impedance shift that has to be accounted for, and the trace is exposed to environmental effects.

Embedded microstrip. Trace on an outer layer buried under a prepreg dielectric, with ground below. Used when additional environmental protection is needed. The additional dielectric above the trace increases effective Dk and lowers impedance compared to standard microstrip at the same trace width.

Stripline. Trace between two ground planes. The default geometry for inner-layer routing. Fully shielded, so it has better crosstalk isolation than microstrip. But it's harder to probe and has slightly higher loss due to the additional ground plane proximity.

Edge-coupled differential. Two traces side by side with controlled spacing. Used for differential pairs on both outer and inner layers. The coupling between traces creates even-mode and odd-mode impedance components. The differential impedance depends on both the individual trace geometry and the coupling factor — which is sensitive to trace spacing, dielectric thickness, and etch profile.

Broadside-coupled differential. Two traces on adjacent layers, vertically aligned. Less common but used when horizontal space is limited. The coupling is through the dielectric between layers rather than through the lateral gap.

Standard material thicknesses: the discrete constraint

One practical reality that surprises engineers new to stack-up design: you can't specify arbitrary dielectric thicknesses. Cores and prepregs come in manufacturer-defined standard thicknesses — and the available values differ by material family.

FR-4 cores are typically available in thicknesses like 0.1 mm, 0.2 mm, 0.36 mm, 0.51 mm, 0.71 mm, 1.0 mm, and 1.6 mm. Prepregs come in specific glass styles — 1080, 2116, 7628, among others — each with a fixed nominal thickness (roughly 0.065 mm, 0.12 mm, and 0.18 mm respectively). You can stack multiple prepreg sheets to reach a target thickness, but only in discrete increments.

RF-grade materials have their own thickness catalogs. Rogers 4350B cores are available in 0.168 mm, 0.254 mm, 0.338 mm, 0.508 mm, and other specific values — not a continuous range. MEGTRON6 has a different set of standard options.

This matters because impedance is directly sensitive to dielectric thickness. If your impedance calculation calls for 0.15 mm of dielectric but the nearest available prepreg is 0.12 mm or 0.18 mm, you have to adjust trace width or accept a different impedance — or change materials entirely. The impedance targeting problem is really a constrained optimization: find a combination of available core thicknesses, available prepreg stacks, and achievable trace widths that hits the target.

Fabs also have preferences. A dielectric thickness achievable in theory (stacking three sheets of 1080 prepreg) may not be a combination your fab routinely processes. Checking with the fab's standard stack-up offerings early in the design avoids surprises during DFM review.

The inverse problem

In practice, designers often work backwards. You know you need 90 ohm differential impedance on a given layer pair. The question is: what trace width, spacing, and dielectric thickness achieve that?

This is the inverse impedance problem, and it's where iteration traditionally happens. An inverse solver takes the target impedance, the material properties, and the layer stack-up as inputs and calculates the required trace geometry — eliminating the trial-and-error loop of adjusting widths and re-running forward calculations.

Inverse solvers have limits, though. They typically assume idealized geometry — perfectly rectangular traces, uniform dielectric, no etch taper. Real fabrication produces trapezoidal cross-sections and slight resin-rich zones near traces, both of which shift impedance from the calculated value. The standard mitigation is to specify impedance tolerances (typically ±10% for general designs, ±5% for high-speed digital, ±3-5% for RF) and accept that the fab will adjust trace widths during DFM to hit the target.

What material compatibility checking looks like

Beyond Dk and Df, practical material selection involves checking several compatibility factors:

  • Tg vs. reflow profile: Will the material survive lead-free reflow (peak ~260°C)? Standard-Tg FR-4 (130°C) is marginal.
  • CTE match: Does the Z-axis CTE of adjacent materials stay within bounds for your reliability class?
  • Moisture absorption: High-moisture materials can cause delamination during reflow (the "popcorn effect").
  • Flammability: UL 94V-0 is required for most applications. Not all specialty laminates carry the rating.
  • Fab availability: Not every fab can process every material. Rogers and PTFE-based laminates require specialized capability.

These checks happen at multiple points in the workflow: initial material selection, internal stack-up review, fab DFM check, and sometimes reliability qualification. The cost of catching a compatibility issue scales sharply with how late it surfaces — minutes during selection, days after a fab quote, weeks if it shows up in a thermal cycling test on a built board.

How do you handle the cost-performance trade-off in material selection? Hybrid stack-ups are the obvious answer, but I'm curious how teams decide where the material boundary goes — which layers get the expensive laminate and which don't.

This is Part 2 of an 8-part series on PCB stack-up design. Previously: "The 7 Domains Behind Every PCB Stack-Up." Next: "Signal Integrity Beyond Impedance."

References

Materials - Rogers Corporation. RO4000 Series High Frequency Circuit Materials — Data Sheet (RO4350B, RO4003C). - Rogers Corporation. RT/duroid 5870/5880 High Frequency Laminates — Data Sheet. - Panasonic Electronic Materials. MEGTRON 4 (R-5725) and MEGTRON 6 (R-5775) Multi-layer Circuit Board Materials — Data Sheets. - Isola Group. I-Tera MT40 Laminate and Prepreg — Product Data Sheet. - Isola Group. Astra MT77 Laminate and Prepreg — Product Data Sheet. - Taconic Advanced Dielectric Division. TLY Series PTFE Laminates — Product Data Sheet.

Impedance and signal integrity - IPC-2141A, Design Guide for High-Speed Controlled Impedance Circuit Boards. IPC. - IPC-D-317A, Design Guidelines for Electronic Packaging Utilizing High-Speed Techniques. IPC.

Tools - MagicON AI. Impedance Calculator. https://pcbgenerator.com/app/impedance-calculator

Manufacturing and reliability - IPC-4101E, Specification for Base Materials for Rigid and Multilayer Printed Boards. IPC. - IPC-2221B, Generic Standard on Printed Board Design. IPC, 2012. - IPC/JEDEC J-STD-020E, Moisture/Reflow Sensitivity Classification for Nonhermetic Surface Mount Devices. IPC/JEDEC.

Safety and flammability - UL 94, Standard for Tests for Flammability of Plastic Materials for Parts in Devices and Appliances. Underwriters Laboratories.