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Signal Integrity Beyond Impedance

Hitting impedance targets is just the beginning. Hitting impedance targets is just the beginning; it is the signal integrity that requires your full attention

We learned two important lessons from our mmWave pcb designs. First, we under-stitched the via walls between channels. The via spacing was too wide for the operating wavelength, and energy leaked through the gaps. As a result, isolation was worse than spec, even though every trace met its impedance target.

On the second, we used a simple roughness correction in the simulator, and the measured insertion loss came in well above what we'd predicted. Same story: impedance was nominally right, but the model under-counted what the copper surface was actually doing at mmWave.

Above a few GHz, impedance is the starting point, not the finish line. Crosstalk, propagation delay, copper roughness loss, and glass weave effects all live in the stackup, and any of them can fail a board that passes impedance.

Here are five signal integrity considerations tied directly to our stackup decisions — including the ones I've watched bite.

  1. Differential pair impedance with etch compensation

Most impedance calculators model traces as perfect rectangles. After etching, real traces have a trapezoidal cross-section — wider at the base, narrower at the top. The etch angle depends on copper weight, etching chemistry, and line width.

For single-ended traces, the impedance shift from etch taper is small. For tightly coupled differential pairs, it matters more. A 5-degree etch angle on an edge-coupled stripline pair can shift differential impedance by 2-3 ohms — enough to push outside a ±5% tolerance window.

On outer layers, soldermask loading adds another 1-2 ohms on microstrip geometries. The 15-20 micron mask changes the effective dielectric environment above the trace, and the thickness varies more than people assume.

Accurate diff pair modeling needs to account for both: trapezoidal etch profiles and soldermask loading on outer layers. In practice, I'll route critical diff pairs on inner stripline layers when I can — it takes the soldermask variable off the table entirely, and the etch profile is more predictable inside the stack.

  1. Crosstalk with multi-aggressor budgets

Nearest-neighbor crosstalk calculations are a useful starting point, but they're incomplete for real bus topologies.

In an 8, 16, or 32-lane data bus, the crosstalk contribution from second and third neighbors adds up. Both near-end crosstalk (NEXT) and far-end crosstalk (FEXT) accumulate. A design that passes a single-aggressor check can fail a multi-aggressor budget by 3-6 dB.

The coupling mechanisms differ between microstrip and stripline. Microstrip has unequal even-mode and odd-mode velocities, which means FEXT doesn't cancel as it does in homogeneous stripline. This makes microstrip routing inherently noisier for parallel bus architectures.

Crosstalk-aware spacing rules derived from multi-aggressor analysis are more conservative than single-pair calculations — typically requiring wider separation, especially for sensitive analog signals where -50 dB isolation may be needed versus -40 dB for digital.

  1. Frequency-dependent propagation delay

Simple propagation delay calculation uses the static dielectric constant: Vp = c / sqrt(Dk). This works below about 5 GHz.

Above 5 GHz, the effective dielectric constant increases with frequency due to dispersion — an effect described by Hammerstad-Jensen and Kirschning-Jansen models. A static-Dk calculation underestimates propagation delay by 5-10% at 10+ GHz.

For timing-critical interfaces like DDR5 (4800 MT/s) or PCIe Gen5 (32 GT/s), that 5-10% error can consume a significant portion of the timing budget.

Two types of skew matter:

Intra-pair skew — within a differential pair. Caused by length mismatch, asymmetric coupling, or dielectric non-uniformity (including glass weave effects, covered below). Protocol specifications typically allow 1-5 ps depending on the interface.

Inter-layer skew — between signals on different layers with different dielectrics. If a bus has some lanes on a microstrip layer and others on a stripline layer, the different effective Dk values create systematic delay differences.

Both types are stackup-dependent and need to be evaluated during stackup design, not after routing.

  1. Copper roughness loss

Above 10 GHz, copper surface roughness becomes a dominant loss mechanism — often exceeding dielectric loss in the total insertion loss budget.

Fabricators roughen the copper surface during lamination to improve adhesion to the dielectric. That roughened surface increases the effective path length for current flow at the skin depth, adding frequency-dependent resistive loss.

The difference between copper treatments is significant:

  • Standard ED foil: RMS roughness 1.5-2.0 microns

  • RTF (reverse treated foil): RMS roughness 1.0-1.5 microns

  • VLP (very low profile): RMS roughness 0.5-1.0 microns

  • HVLP (hyper very low profile): RMS roughness < 0.5 microns

At 28 GHz, HVLP can reduce conductor loss by 30-40% compared to standard ED. But HVLP costs 3-5x more and has lower peel strength (adhesion to the dielectric), which can be a reliability concern.

These trade-offs have to be managed well.

Two models are commonly used for roughness correction:

Hammerstad-Bekkadal — a classical correction factor based on RMS roughness versus skin depth. Accurate up to roughly 20 GHz, where it begins to underestimate loss because it doesn't capture the fractal nature of real surface roughness.

Huray snowball model — represents the rough surface as an array of hemispheres on a flat plane. More physically accurate at mmWave frequencies (28+ GHz) because it better models the current path distortion around individual surface features.

Knowing where roughness loss overtakes dielectric loss for your specific material and frequency helps justify the cost premium for smoother copper — or confirms that it's unnecessary.

  1. Glass weave Dk variation

This one catches experienced engineers by surprise.

Standard FR-4 and most high-frequency laminates use woven fiberglass reinforcement. The weave creates a periodic pattern of glass-rich and resin-rich regions with different dielectric constants. The Dk variation is typically 0.3-0.5 for standard weave styles like 1080 or 2116.

When one trace of a differential pair sits over a glass-rich region and the other over a resin-rich region, the Dk asymmetry causes intra-pair skew. At 28+ Gbps signaling rates, this glass-weave-induced skew can consume a meaningful portion of the timing budget. PCB stackup designers have to be mindfull of these effects.

Several mitigation approaches exist:

Spread glass weave styles — 1067 and 1078 use flattened, evenly distributed fibers that reduce Dk variation by 5-10x compared to standard weaves. This is the most effective solution but adds material cost.

Routing angle. Routing traces at 10-15 degrees off the warp/fill axis averages out the periodic Dk variations. Effective when spread glass isn't available, though it complicates routing and may not be practical for dense designs.

Orthotropic Dk awareness. The dielectric constant differs in the warp versus fill direction of the weave. This means routing direction affects propagation delay — a consideration for designs where traces run long distances in a single direction.

The integrated picture

These five effects interact. Changing a dielectric thickness to fix impedance shifts crosstalk coupling, propagation delay, and the frequency at which roughness loss becomes dominant. Selecting a different copper foil changes insertion loss and peel strength. Choosing a spread glass prepreg affects both Dk uniformity and resin flow.

Ideally, we need simulations/calculations that share the same stackup model and update simultaneously — impedance, crosstalk, delay, and loss all recalculate when any parameter changes. The goal is to make these interactions visible during design rather than discovering them one at a time across separate tools.

Which of these five has caused the most unexpected failures in your experience? Glass weave skew seems to be the one that catches people off guard most often, but I'd be curious to hear otherwise.

This is Part 3 of an 8-part series. Previously: "Material Selection and Impedance Targeting." Next: "Power Integrity Starts in the Stackup."

References

  1. Hammerstad, E., and Jensen, O. "Accurate Models for Microstrip Computer-Aided Design." IEEE MTT-S International Microwave Symposium Digest, 1980, pp. 407-409.

  2. Kirschning, M., and Jansen, R. H. "Accurate Wide-Range Design Equations for the Frequency-Dependent Characteristic of Parallel Coupled Microstrip Lines." IEEE Transactions on Microwave Theory and Techniques, vol. 32, no. 1, 1984, pp. 83-90.

  3. Hammerstad, E., and Bekkadal, F. "A Microstrip Handbook." ELAB Report STF44 A74169, University of Trondheim, Norway, 1975.

  4. Huray, P. G. The Foundations of Signal Integrity. Wiley-IEEE Press, 2009. (Snowball roughness model.)

  5. Huray, P. G., Pytel, S., Oluwafemi, F., Mellitz, R., Hua, X., and Ye, P. "Fundamentals of a 3-D Snowball Model for Surface Roughness Power Losses." IEEE Workshop on Signal Propagation on Interconnects, 2007.

  6. Bogatin, E. Signal and Power Integrity — Simplified, 3rd ed. Prentice Hall, 2018. (Crosstalk, NEXT/FEXT, multi-aggressor budgeting.)

  7. Coonrod, J. "Insertion Loss Comparisons of Common High-Frequency PCB Constructions." Rogers Corporation Technical Paper, 2013. (Conductor roughness vs. dielectric loss trade-offs.)

  8. IPC-2141B. "Design Guide for High-Speed Controlled Impedance Circuit Boards." IPC, 2024. (Etch compensation, trapezoidal trace modeling, soldermask loading.)

  9. IPC-4101F. "Specification for Base Materials for Rigid and Multilayer Printed Boards." IPC, 2021. (Glass weave styles, including 1067/1078 spread-glass.)

  10. Loyer, J., Kunze, R., and Ye, X. "Fiber Weave Effect: Practical Impact Analysis and Mitigation Strategies." DesignCon, 2007.

  11. JEDEC JESD79-5C. "DDR5 SDRAM Standard." JEDEC Solid State Technology Association, 2024. (Timing budget for 4800+ MT/s interfaces.)

  12. PCI-SIG. "PCI Express Base Specification, Revision 5.0." PCI Special Interest Group, 2019. (32 GT/s timing and skew requirements.)