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Power Integrity Starts in the Stackup

Power integrity analysis is usually treated as a downstream activity — something you do after the stackup is finished, often with a separate tool.

But the stackup is the PDN baseline. The power/ground plane pairs, their separation, their dielectric properties, and their overlap area define the interplanar capacitance that serves as your first line of high-frequency decoupling. Every stackup decision has a PDN consequence.

This article covers how PDN impedance analysis connects to stackup design and why the two shouldn't be separated.

Interplanar capacitance: free decoupling

Every power/ground plane pair in the stackup is a parallel-plate capacitor. The capacitance is determined by three stackup parameters:

  • Overlap area between the planes
  • Dielectric thickness separating them
  • Dielectric constant of the material between them

A pair of planes separated by 4 mils of FR-4 (Dk = 4.2) over a 100 cm² area gives approximately 9.3 nF of distributed capacitance. That's decoupling with no BOM cost and no board area consumed — but only if you design for it.

This interplanar capacitance provides charge storage at frequencies where discrete decoupling capacitors lose effectiveness due to parasitic inductance. A typical 100 nF MLCC with 1 nH mounting inductance self-resonates around 500 MHz — above that frequency, it looks inductive rather than capacitive. The plane pair capacitance takes over in this range.

The practical implication: moving a power plane closer to its reference ground increases the interplanar capacitance and extends its effective frequency range. Moving it farther away — perhaps to accommodate a signal layer — reduces it.

Target impedance

The fundamental PDN design criterion is that the impedance at any frequency must stay below a target value determined by three parameters:

Z_target = V_supply × tolerance / I_transient

For a 1.0V rail with 5% tolerance and 2A transient current draw: Z_target = (1.0 × 0.05) / 2.0 = 25 milliohms.

This target must be met from DC up to the maximum frequency of the transient current — which for modern FPGAs and processors can extend to several GHz.

A proper PDN analysis builds the frequency-domain impedance profile Z(f) from DC to multi-GHz, incorporating:

  • VRM output impedance (dominant at low frequencies, typically below 100 kHz)
  • Bulk capacitor network (effective from ~10 kHz to ~10 MHz)
  • MLCC decoupling (effective from ~1 MHz to ~500 MHz, limited by mounting inductance)
  • Interplanar capacitance (effective above ~100 MHz, determined by the stackup)

Overlaying the target impedance line on the Z(f) curve immediately shows which frequency ranges are problematic.

Resonance: the hidden failure mode

The Z(f) profile isn't smooth. At frequencies where inductive and capacitive elements resonate, impedance spikes can exceed the target by an order of magnitude.

A resonance at a frequency where the IC draws significant transient current means voltage droop, power rail ringing, and potentially functional failure. The board may pass every signal integrity check and still malfunction because of a PDN resonance that nobody plotted.

Common resonance sources:

  • Anti-resonance between capacitor groups. The parallel combination of bulk capacitors and MLCCs creates a resonance peak at the frequency where one group transitions from capacitive to inductive. This peak sits between the effective ranges of the two groups.
  • Plane resonance. The power/ground plane pair resonates at frequencies determined by the board dimensions and dielectric properties — essentially a cavity resonator. For a 10 cm × 10 cm board with Dk = 4.2, the first resonance is around 750 MHz.

Both types are visible in the Z(f) curve and addressable through capacitor selection and stackup adjustment.

Decoupling optimization

Once the Z(f) profile is constructed and resonance peaks are identified, the next step is selecting decoupling capacitors to flatten the impedance below the target.

This is more nuanced than "add more 100 nF caps." Effective decoupling optimization considers:

  • Capacitor value selection — different values resonate at different frequencies, providing broad frequency coverage
  • ESR and ESL specifications — the parasitic resistance damps resonance peaks; the parasitic inductance determines the upper frequency limit
  • Mounting inductance — the PCB pad geometry and via structure add inductance that shifts the effective frequency range downward
  • Quantity and placement — more capacitors in parallel reduce impedance, but with diminishing returns due to mutual inductance

The optimizer's output is a recommended network: specific capacitor values, quantities, and ESR/ESL specs, along with the resulting Z(f) curve showing where the impedance now falls relative to the target.

The stackup connection

Here's why this belongs in the stackup tool rather than a separate analysis:

When you adjust a dielectric thickness to fix an impedance target on a signal layer, you may simultaneously change the separation between a power/ground plane pair. That changes the interplanar capacitance, which shifts the Z(f) curve, which may create or move a resonance peak.

When you add a signal layer between a power/ground pair to gain routing resources, you increase the plane separation and reduce the interplanar capacitance — weakening the high-frequency PDN.

When you move a power plane to improve symmetry (reducing warpage), you change its distance to the reference ground — affecting PDN impedance.

These are routine stackup decisions with PDN consequences that are invisible if the tools are separate.

In MagicON AI, the PDN impedance profile updates in real time as the stackup changes. Move a plane, and the Z(f) curve and decoupling recommendations update alongside the signal impedance results. The trade-offs between signal integrity and power integrity are visible in the same view.

Have you ever traced a functional failure back to a PDN resonance? It's a particularly frustrating debugging experience because the board can look electrically "correct" by every other measure.

This is Part 4 of an 8-part series. Previously: "Signal Integrity Beyond Impedance." Next: "Thermal Engineering in the Stackup."