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Thermal Engineering in the Stackup

When engineers think about PCB stackup design, they think impedance, materials, maybe signal integrity. Thermal management rarely enters the conversation until after the board comes back from fab and something overheats.

But the stackup defines the thermal path. The copper layers, dielectric thicknesses, via structures, and material properties collectively determine how heat moves through the board — from junction to ambient. Every stackup decision has a thermal consequence.

This article covers the five thermal calculations that are directly tied to the stackup.

Thermal via resistance

High-power components — power amplifiers, voltage regulators, radar MMICs — dissipate significant heat through the PCB. The primary conduction path runs through thermal vias underneath the component, from the thermal pad down through the board to a ground plane or heatsink on the opposite side.

The thermal resistance of a via array depends on several parameters: via diameter, copper plating thickness, fill material (air, epoxy, or copper), via count, and total board thickness. A single 0.3 mm via with 25 micron plating through a 1.6 mm board has roughly 70°C/W thermal resistance. An array of 25 such vias in parallel drops that to about 3°C/W — a practical number for moderate-power components.

Fill material matters more than most engineers expect. A copper-filled via has roughly 10x lower thermal resistance than an air-filled via of the same dimensions. For components dissipating more than 2-3 watts, filled vias are often necessary to keep junction temperatures within the safe operating area.

The via-to-pad interface adds constriction resistance — heat funneling from the component pad into the smaller via barrel. This constriction term can account for 15-25% of the total via array Rth, particularly for components with large thermal pads and small vias.

The junction-to-ambient chain

A single thermal resistance number is meaningless without context. What matters is the complete thermal resistance chain from the semiconductor junction to the ambient environment:

  • Junction to case (Rth_jc) — from the component datasheet. Typically 1-20°C/W depending on package type.
  • Case to board surface (Rth_cb) — determined by the thermal interface material or direct solder contact. Typically 0.5-5°C/W.
  • Through the via array (Rth_via) — calculated from the stackup as described above.
  • Board surface to ambient (Rth_ba) — convection and radiation from the board surface. Highly dependent on airflow and enclosure design.

The steady-state junction temperature is: T_junction = T_ambient + P_dissipated × (Rth_jc + Rth_cb + Rth_via + Rth_ba).

For a PA dissipating 3W with a total thermal resistance chain of 40°C/W in a 40°C ambient environment: T_junction = 40 + 3 × 40 = 160°C. If the component's maximum junction temperature is 150°C, the design fails — and the fix has to come from somewhere in the stackup.

Options include adding more vias, switching to copper-filled vias, or reducing board thickness. All of these are stackup decisions that interact with impedance, layer assignment, and mechanical constraints.

Copper pour heat spreading

Heat doesn't flow straight down through vias. It spreads laterally through copper planes. The effectiveness of this spreading depends on copper area, thickness, and the thermal conductivity contrast between copper (~400 W/mK) and the surrounding dielectric (~0.3 W/mK).

Kennedy spreading resistance quantifies the additional thermal resistance that comes from heat spreading outward from a small source into a larger copper pour. For a 5 mm × 5 mm component pad above a ground plane that extends 50 mm in each direction, the spreading resistance accounts for the geometric transition from the concentrated heat source to the distributed copper area.

This term is often overlooked, but it can represent 30-50% of the total board-level thermal resistance — particularly for small-pad packages like QFN mounted above large ground planes. The spreading resistance depends on the copper layer thickness: a 2 oz copper plane spreads heat more effectively than a 0.5 oz plane, reducing the spreading resistance component.

Barrel stress and via reliability

Thermal cycling creates mechanical stress in plated through-hole vias. The copper barrel and the surrounding dielectric expand at different rates — copper at roughly 17 ppm/°C, while FR-4's Z-axis CTE ranges from 40-70 ppm/°C above the glass transition temperature. Over hundreds or thousands of temperature cycles, this differential expansion fatigues the copper barrel, eventually causing cracks and open circuits.

The Coffin-Manson fatigue model predicts cycles-to-failure from the CTE mismatch, temperature excursion range, copper plating thickness, and board thickness. The relationship is nonlinear — doubling the temperature excursion range more than halves the fatigue life.

Application classes set the bar:

  • Consumer electronics: ~500 thermal cycles (-20°C to +60°C)
  • Industrial: ~1,000 cycles (-40°C to +85°C)
  • Automotive: ~3,000 cycles (-40°C to +125°C)
  • Military/aerospace: 5,000+ cycles (-55°C to +125°C)

For automotive and military applications, the combination of wide temperature range and high cycle count demands careful attention to plating thickness (minimum 25 micron for IPC-6012 Class 3), material selection (lower Z-axis CTE), and board thickness (thinner boards have shorter barrels with less total strain).

These calculations are stackup-dependent: changing the dielectric material changes the CTE, changing the board thickness changes the barrel length, and both affect the predicted fatigue life.

Warpage prediction

A stackup with asymmetric copper distribution — more copper on the top than the bottom, or different dielectric thicknesses above and below the midplane — will warp during lamination and reflow. Warpage causes BGA solder joint failures, connector misalignment, and assembly yield loss.

The Timoshenko bimetallic strip model, adapted for multi-layer PCBs, predicts warpage from each layer's modulus of elasticity, CTE, thickness, and position relative to the neutral axis. The key insight is that warpage is primarily driven by asymmetry — not absolute copper weight, but the difference in copper distribution between the top half and bottom half of the stackup.

IPC-6012 limits warpage to 0.75% for standard boards — meaning a 100 mm board can bow no more than 0.75 mm. For BGA assemblies, the practical limit is often tighter because the solder joints are intolerant of board curvature during reflow.

Addressing warpage is straightforward in principle: add dummy copper fills on copper-light layers, adjust layer thicknesses to balance the stackup about the midplane, or select materials with matched CTE. In practice, these adjustments interact with impedance targets and routing constraints, which is why warpage prediction needs to be part of the stackup design process rather than a post-manufacturing surprise.

Resin flow

During lamination, prepreg layers soften and flow to fill gaps around traces and vias. Insufficient resin flow causes voids and delamination. Excessive flow causes resin starvation on adjacent layers.

The required resin volume depends on copper coverage — layers with dense copper routing have less gap volume to fill and need less resin, while layers with sparse copper need high-resin-content prepreg to fill the larger gaps. Standard prepreg resin content ranges from about 50% to 70% by weight.

Selecting the wrong resin content for your copper density is a common manufacturing failure mode. A high-copper-density layer paired with high-resin-content prepreg can cause excess resin squeeze-out. A low-copper-density layer paired with low-resin prepreg results in voids.

The calculation is stackup-specific: the copper coverage on each layer determines the gap volume, which determines the required resin content for the adjacent prepreg. It's a manufacturing consideration that's best addressed during stackup design rather than discovered during fab DFM review.

Have you had a board come back with warpage or barrel cracking that traced back to a stackup asymmetry or material choice? These failures are particularly frustrating because they're predictable — with the right calculations during design.

In MagicON AI, the thermal analysis suite — via Rth, spreading resistance, barrel stress, warpage, and resin flow — runs alongside impedance and signal integrity calculations, updating as the stackup changes. The trade-offs between electrical and thermal performance are visible in the same view.

This is Part 5 of an 8-part series. Previously: "Power Integrity Starts in the Stackup." Next: "Compliance Checking for PCB Stackups."