Test Coupons and Export Formats¶
A stackup design isn't complete when the calculations check out. It's complete when the fab has everything they need to build it correctly — and when there are structures on the panel to verify that they did.
Test coupons and export formats are the bridge between design and manufacturing. They're often treated as an afterthought, but they determine whether your carefully engineered stackup actually gets built to spec.
Test coupons: manufacturing verification
Fabs verify controlled-impedance boards using test coupons — dedicated structures placed on the manufacturing panel, measured with TDR (Time Domain Reflectometry), and then discarded when the panel is depaneled.
Three types of coupon specifications tie directly to the stackup:
TDR impedance coupon structures. For every controlled-impedance geometry in the stackup — single-ended microstrip at 50 ohms on Layer 1, differential stripline at 100 ohms on Layers 3-4 — a corresponding test coupon must be defined. Each coupon needs: trace width matching the production geometry, spacing matching the production differential pair, a length sufficient for TDR measurement (typically 150 mm / 6 inches), ground plane references matching the production layer, and launch pad geometry compatible with the TDR probe.
The critical requirement is that the coupon must replicate the exact stackup conditions of the production trace. A coupon built on a different layer pair or with a different dielectric reference doesn't verify the production impedance — it verifies something else entirely. This is a common source of false confidence: the coupon passes, but it doesn't actually represent the production geometry.
Microsection specification documents. Cross-sectional analysis (microsectioning) is the definitive method for verifying dielectric thickness, copper weight, plating quality, and layer registration. A microsection spec tells the fab: where to cut the panel, what features to measure (dielectric thickness between specific layers, copper plating thickness in through-holes, annular ring dimensions), and what the acceptance criteria are.
The acceptance criteria come directly from the compliance check — IPC-6012 Class 2 has different plating thickness requirements than Class 3. Linking the microsection spec to the compliance results ensures consistency between what you're checking and what the standard requires.
Impedance tables for fab submission. Every fab needs a clear impedance table: net class name, target impedance, tolerance (typically ±10% for commercial, ±5% for high-reliability), trace width, trace spacing (for differential), reference layers, dielectric thickness, and the corresponding coupon ID.
Compiling this table manually from the stackup design is tedious and error-prone — especially for complex stackups with multiple impedance classes across different layer pairs. Generating it directly from the stackup definition eliminates transcription errors and ensures the table matches the actual design.
Export formats: the manufacturing interface
The PCB industry uses multiple export formats because no single format serves all downstream tools. A stackup design may need to reach a fabricator, a simulation tool, a layout editor, and a documentation archive — each expecting a different format.
Eight formats cover the practical landscape:
ODB++ — direct fab submission. The de facto standard for advanced fabricators. ODB++ is a structured directory format that captures layer stackup, drill data, copper geometry, and manufacturing notes in a single archive. Most high-capability fabs prefer ODB++ over Gerber because it contains explicit layer relationships and stackup definitions rather than requiring the fab to reconstruct them from individual Gerber files.
Gerber — universal manufacturing format. The lowest-common-denominator format that every fab accepts. Gerber files describe copper geometry layer by layer, with separate files for drills, soldermask, and silkscreen. The limitation is that Gerber has no native stackup representation — the stackup must be communicated separately, usually in a fabrication drawing or README file.
IPC-2581 — the emerging standard. An XML-based format designed to replace the combination of Gerber + drill files + fab notes with a single, self-describing file. IPC-2581 includes explicit stackup definitions, material callouts, impedance requirements, and manufacturing instructions. Adoption is growing but not yet universal.
KiCad — open-source EDA integration. Native KiCad project files for teams using the open-source EDA workflow. The export creates a board file with the stackup layer definitions, design rules, and impedance-class net assignments configured — ready for layout without manual stackup entry.
Keysight ADS — RF simulation. Substrate definition files with the layer stack, material properties (Dk, Df at frequency), and copper specifications configured for ADS electromagnetic simulation. This allows RF engineers to simulate transmission line behavior on the exact stackup without manually recreating the layer stack in the simulator.
Ansys HFSS — 3D electromagnetic simulation. PyAEDT script generation that builds the stackup geometry in HFSS for full-wave 3D simulation. Used for via transitions, connector launches, and other structures where 2D approximations are insufficient.
PDF — documentation and fab specification. A formatted stackup drawing with material callouts, layer assignments, impedance targets, drill specifications, and notes. Designed for human consumption — fab engineers, design reviewers, and program managers who need to understand the stackup without opening an EDA tool.
Internal JSON — design re-import. A complete design state file that captures not just the stackup geometry but the full analysis context: solver results, material selections, compliance status, and design parameters. Used for design versioning, re-import, and iteration across sessions.
Sidecar metadata: preserving design intent
Traditional exports carry the what — layer thicknesses, materials, trace widths — but never the why. When a fab engineer asks "why is this trace 5 mil wide on Layer 3?", the answer is typically buried in an email thread, a design review slide deck, or the original engineer's memory.
A sidecar metadata file (structured JSON exported alongside every format) captures the engineering reasoning:
- Impedance targets and solver results for every controlled-impedance geometry
- Material selection rationale — why one material was chosen over another
- Design constraints and trade-off decisions
- Compliance check results with pass/fail per applicable standard
- A deterministic stackup fingerprint (SHA-256 hash of the canonical layer configuration)
The fingerprint is particularly useful for traceability. It provides a unique identifier for each specific stackup configuration that can link the design to its manufacturing outcomes — yield data, test results, and process notes — across projects and over time.
When someone inherits a project six months later, the sidecar file tells them not just what the stackup is, but why it is that way. The design intent travels with the files rather than evaporating when the original engineer moves to another project.
The gap between design and manufacturing
The recurring problem in PCB manufacturing is incomplete information transfer. The designer knows why every parameter was chosen. The fab sees only the final numbers. When something doesn't quite work — an impedance target that's marginally achievable, a material substitution that seems equivalent — the fab makes a judgment call without the context that would inform it.
Test coupons that precisely match production geometries, export formats that carry explicit stackup definitions, and metadata that preserves design reasoning all address this gap from different angles.
How much time does your team spend compiling impedance tables and test coupon specs for fab submission? For complex stackups with multiple impedance classes, it can consume a surprising amount of engineering time — time that adds no design value.
In MagicON AI, test coupon specifications, impedance tables, and all eight export formats generate directly from the stackup definition. Sidecar metadata exports automatically alongside every format.
This is Part 7 of an 8-part series. Previously: "Compliance Checking for PCB Stackups." Next: "Design Intelligence and Manufacturing Yield."