Integration: From Block Diagram to Working Hardware¶
Selecting the right components is half the job. Making them work together on a real PCB — with real parasitics, real thermal constraints, and real manufacturing tolerances — is the other half.
This final article covers what happens after component selection: inter-stage matching, bias design, PCB layout for RF, and the test strategy that catches problems before they become production failures.
Inter-stage matching: the glue between blocks
Every component-to-component interface in a transmitter chain is an impedance matching problem. Datasheets characterize components at 50 ohms. Real inter-stage interfaces often aren't 50 ohms.
S-parameter-based matching. Proper matching design starts with S-parameter files (.s2p) from component vendors. The source impedance (S22 of the upstream component) and load impedance (S11 of the downstream component) define the matching requirement. At 3.5 GHz, a PA's input impedance might be 15 + j8 ohms. Matching this to 50 ohms requires a two-element network — but the exact topology and values depend on the specific impedance transformation needed.
Narrowband vs. wideband matching. A simple L-network (two reactive elements) matches perfectly at a single frequency but rolls off across bandwidth. For a 100 MHz channel, that's usually fine. For a 400 MHz 5G NR bandwidth, a more complex network (Pi, T, or multi-section) is needed to maintain acceptable match across the band. Each additional matching element adds insertion loss — typically 0.1-0.3 dB per element at GHz frequencies.
Source and load pull. For the PA output match, the optimal load impedance isn't the conjugate match (which maximizes power transfer) — it's the impedance that achieves the best trade-off between output power, efficiency, and linearity. Load-pull measurements (or simulations) sweep the PA's load impedance and plot contours of constant power, efficiency, and ACLR. The designer then selects a load impedance that sits in the overlap region of acceptable contours. This load impedance is typically different from the conjugate match.
Bias design and sequencing
RF components require specific DC bias conditions to operate correctly. Getting the bias wrong ranges from suboptimal performance to permanent device damage.
PA bias. Power amplifiers typically require gate bias (for GaN FETs: -2 to -3 V) and drain bias (+28 V for GaN, +5 V for GaAs). The gate bias sets the quiescent current, which determines the PA class (Class A, AB, B). A 10 mV change in gate bias can shift the quiescent current by 50 mA, changing the PA's linearity and efficiency characteristics.
Bias sequencing. Many GaN PAs require the gate bias to be applied before the drain voltage — applying drain voltage to an unbiased gate can cause excessive current draw and device failure. The power-up sequence is typically: (1) apply negative gate bias, (2) apply drain voltage, (3) adjust gate bias to target quiescent current. Power-down is the reverse. This sequencing requires a dedicated bias control circuit or a sequencing controller IC.
Temperature compensation. PA quiescent current drifts with temperature. Without compensation, a PA biased for optimal linearity at 25C may be over-biased (excessive current, risking thermal runaway) at 85C or under-biased (poor linearity) at -40C. Active bias circuits using a temperature sensor and feedback loop maintain stable quiescent current across temperature.
Supply regulation. The PA's supply voltage directly affects output power. A 0.5 V drop on a 5 V supply (10% variation) reduces output power by approximately 1 dB. Low-dropout regulators (LDOs) or DC-DC converters with tight regulation (< 2% load regulation) are necessary for consistent performance.
PCB layout for RF transmitters
RF PCB layout is where electromagnetic theory meets manufacturing reality. Mistakes here create problems that no amount of component optimization can fix.
Grounding. Continuous, uninterrupted ground planes are the foundation of RF PCB design. Every signal via should have adjacent ground vias — the ground return path must be as short and low-inductance as possible. A signal via without nearby ground vias creates a slot in the ground plane that radiates, increases inductance, and degrades return loss. For the PA and driver, ground via arrays under the exposed pad provide both thermal and electrical grounding.
Trace routing. Transmission lines (microstrip or stripline) must maintain controlled impedance. A 50 ohm microstrip on 8 mil FR-4 is approximately 15 mils wide. Bends, width transitions, and via transitions all introduce discontinuities. Right-angle bends are avoided — 45-degree miters or curved bends reduce reflections. Via transitions between layers require attention to the ground return path — a signal via transitioning from microstrip to stripline needs ground vias on both sides to maintain the return current path.
Component placement. The transmitter chain should be laid out in a logical signal flow path — mixer to filter to driver to PA to output. Minimize the trace length between stages. Keep the PA as close to the board edge and antenna connector as possible to minimize output trace loss. Place bypass capacitors within 1-2 mm of device power pins — the inductance of a 3 mm trace to a bypass cap negates its effectiveness above 1-2 GHz.
Isolation. The PA output can be 50-60 dB above the mixer output level. If PA output energy couples back to the mixer or driver input, oscillation results. Physical separation, shielding (metal cans or fence vias), and careful routing prevent this. On a dense board, EMI fence vias — rows of ground vias between sections — provide 20-30 dB of isolation between adjacent RF sections.
Thermal layout. The PA's exposed thermal pad requires a via array connecting to internal ground planes and ideally to a bottom-side copper pour or heatsink pad. Via diameter, pitch, and fill material (copper-filled vias provide the lowest thermal resistance) all affect the thermal path. Simulate the thermal performance — or at minimum, calculate the junction temperature using the thermal resistance chain — before committing to a layout.
Test strategy
A transmitter that meets specs on paper must be verified on hardware. The test strategy should be planned during design — not improvised after the first prototype arrives.
Essential transmitter measurements:
Output power. Measure at the antenna connector with a calibrated power meter. Verify across the full frequency band, temperature range, and power control range. Compare to the link budget prediction — discrepancies indicate matching or gain problems.
EVM (Error Vector Magnitude). Requires a vector signal analyzer (VSA) and the appropriate modulation standard loaded. EVM captures the combined effects of phase noise, amplitude distortion, I/Q imbalance, and noise floor. It's the single most comprehensive measurement of transmitter signal quality.
ACLR (Adjacent Channel Leakage Ratio). Measured with a spectrum analyzer using the standard-defined measurement bandwidth and offset. ACLR is the regulatory compliance measurement — failing ACLR means the product can't ship.
Harmonic power. Second and third harmonics measured at the antenna port. Compare to the regulatory emission mask limits. If harmonics are too high, the output filter needs more rejection.
Spurious emissions. Wideband scan from 9 kHz to at least 5x the operating frequency, looking for unexpected emissions. Mixer spurs, oscillator harmonics, digital clock harmonics, and supply switching noise can all appear in the output spectrum.
Stability. Verify no oscillations across the full operating temperature range, supply voltage range, and load VSWR range. Use a spectrum analyzer with wide span (DC to several GHz above the operating frequency) and look for unexpected spectral lines. Oscillations that appear only at specific temperatures or load conditions are particularly insidious.
Bringing it all together
RF transmitter design is fundamentally a systems engineering problem. No single component specification guarantees system performance — it's the interaction between components, the matching networks connecting them, the bias conditions controlling them, the PCB routing supporting them, and the thermal management sustaining them.
The sequential dependency from Part 1 reappears at every stage. A PA change requires re-evaluating the driver, the matching networks, the thermal design, and the link budget. A VCO change affects the mixer's spur spectrum, which affects the filter requirement, which affects the insertion loss budget.
This is why experienced RF engineers iterate. The first pass through the design identifies the major constraints. The second pass optimizes within those constraints. The third pass resolves the interactions between optimizations. The goal isn't to get it right the first time — it's to converge efficiently.
What's been the most surprising integration issue you've encountered in a transmitter build? For me, it was discovering that a PA's output matching, which was perfect on the evaluation board, shifted significantly when transplanted to our product PCB due to different stackup dielectric thickness. A reminder that the PCB is part of the circuit.
This is Part 8 of an 8-part series on RF transmitter design. The complete series: [1] Transmitter Anatomy, [2] VCO Selection, [3] Mixer & Upconversion, [4] Filter Selection, [5] Driver Amplifiers, [6] Power Amplifiers, [7] Link Budget Analysis, [8] Integration.